[Solved]6 Write Vhdl Stdlogic Code Description Counter Following Sequence 9 12 10 4 7 Repeat Libra Q37242045

6. Write a VHDL std_logic code description for a counter with the following sequence: 9,12,10, 4, 7 then repeat library IEEE; use IEEE.STD LOGIC 1164.ALL use IEEE. STD LOGIC ARITH. ALL; use IEEE . STD LOGIC UNSIGNED·ALL; entity partl is Port ( end partl; architecture Behavioral of partl is TYPE states is (nine, twelve,ten, four, seven) signal current_state,next state: states; begin Q<=”000″; process (current state,clk) if then case when when when when when end process; with select Q< current-state “when 4 IT 7 10 –12 “when when when end Behavioral; Show transcribed image text 6. Write a VHDL std_logic code description for a counter with the following sequence: 9,12,10, 4, 7 then repeat library IEEE; use IEEE.STD LOGIC 1164.ALL use IEEE. STD LOGIC ARITH. ALL; use IEEE . STD LOGIC UNSIGNED·ALL; entity partl is Port ( end partl; architecture Behavioral of partl is TYPE states is (nine, twelve,ten, four, seven) signal current_state,next state: states; begin Q

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Answer to 6. Write a VHDL std_logic code description for a counter with the following sequence: 9,12,10, 4, 7 then repeat library … . . .