[Solved]-Uestion 1 1 Point Following Statements Describe Mips Pipeline Select True Statements Instr Q37208358

uestion 1 (1 point) The following statements describe the MIPS pipeline. Select all the TRUE statements In the instruction fetch (IF) stage, the instruction is loaded into instruction memory. In MIPS pipeline, there are five stages, i.e. Instruction fetch (IF), Instruction decode (ID) Execute operation (EX), Access memory operand (MEM) and Write result back (WB). R-type instructions are able to store the result of the arithmetic logic operation in the access memory operand (MEM) stage. In the execute operation (EX) stage, ALU is used to execute the logic operation or calculate the memory address. Question 2 (1 point) Saved We examine how pipelining affects the clock cycle time of the processor. Problems in this quiz assume that individual stages of the datapath have the following latencies: WB EX MEM ID IF 100 ps 150 ps 200 ps 100 ps 150 ps What is the clock cycle of a pipelined processor (assume no stall or hazard)? 700 ps 150 ps e 100 ps 200 ps uestion 3 (1 point) Individual stages of the datapath have the following latencies: WB MEM EX ID IF 100 ps 200 ps 150 ps 100 ps 150 ps What is the total latency of five LW instructions in a pipelined processor (assume no stalls or hazards)? 1800 ps 2400 ps 1600 ps 2000 ps Show transcribed image text uestion 1 (1 point) The following statements describe the MIPS pipeline. Select all the TRUE statements In the instruction fetch (IF) stage, the instruction is loaded into instruction memory. In MIPS pipeline, there are five stages, i.e. Instruction fetch (IF), Instruction decode (ID) Execute operation (EX), Access memory operand (MEM) and Write result back (WB). R-type instructions are able to store the result of the arithmetic logic operation in the access memory operand (MEM) stage. In the execute operation (EX) stage, ALU is used to execute the logic operation or calculate the memory address. Question 2 (1 point) Saved We examine how pipelining affects the clock cycle time of the processor. Problems in this quiz assume that individual stages of the datapath have the following latencies: WB EX MEM ID IF 100 ps 150 ps 200 ps 100 ps 150 ps What is the clock cycle of a pipelined processor (assume no stall or hazard)? 700 ps 150 ps e 100 ps 200 ps
uestion 3 (1 point) Individual stages of the datapath have the following latencies: WB MEM EX ID IF 100 ps 200 ps 150 ps 100 ps 150 ps What is the total latency of five LW instructions in a pipelined processor (assume no stalls or hazards)? 1800 ps 2400 ps 1600 ps 2000 ps

Expert Answer

---

Answer to uestion 1 (1 point) The following statements describe the MIPS pipeline. Select all the TRUE statements In the instructi… . . .