[Solved] 2 Way Set Associative L1 Cache 8kb 4 Word Cache Lines Get Following Sequence Writes Cache Q37163318

You have a 2-way set associative L1 cache that is 8KB,with 4-word cache lines. You get the following sequence of writesto the cache — each is a 32-bit address inhexadecimal:

0x32E4

0x8000

0x1F50

0x8004

0x72EC

0xD00C

0x800C

0x72E8

0x4008

0xD000

0x82E0

a) [7 Pts] How many cache misses occur with an MRU (MostRecently Used) policy? Give a detailed answer and fill in the tablebelow for each address reference.

Memory Address

Tag (in hex)

Set Index (in hex)

Hit/Miss

Data to be placed in set …way …

0x32E4

0x8000

Expert Answer

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Answer to You have a 2-way set associative L1 cache that is 8KB, with 4-word cache lines. You get the following sequence of writes… . . .