[Solved] 2 Way Set Associative L1 Cache 8kb 4 Word Cache Lines Get Following Sequence Writes Cache Q37156666

You have a 2-way set associative L1 cache that is 8KB, with 4-word cache lines. You get the following sequence of writes to the cache –each is a 32-bit address in hexadecimal 0x32E4 0x8000 0x1F50 0x8004 0x72EC OxDOOC 0x800C 0x72E8 0x4008 OxD000 0x82E0 a) [7 Pts] How many cache misses occur with an LFU (Least Frequently Used) policy? Give a detailed answer and fill in the table below for each address reference Set Index (in hex) Memory address(in hex) 0x32E4 0x8000 Tag Hit/Miss Data to be placed in set .. way… b) 3 Pts] For part (a) indicate the type of miss (compulsory, conflict, capacity)for each address reference Hit/Miss Memory address 0x32E4 0x8000 Type of miss Show transcribed image text You have a 2-way set associative L1 cache that is 8KB, with 4-word cache lines. You get the following sequence of writes to the cache –each is a 32-bit address in hexadecimal 0x32E4 0x8000 0x1F50 0x8004 0x72EC OxDOOC 0x800C 0x72E8 0x4008 OxD000 0x82E0 a) [7 Pts] How many cache misses occur with an LFU (Least Frequently Used) policy? Give a detailed answer and fill in the table below for each address reference Set Index (in hex) Memory address(in hex) 0x32E4 0x8000 Tag Hit/Miss Data to be placed in set .. way… b) 3 Pts] For part (a) indicate the type of miss (compulsory, conflict, capacity)for each address reference Hit/Miss Memory address 0x32E4 0x8000 Type of miss

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Answer to You have a 2-way set associative L1 cache that is 8KB, with 4-word cache lines. You get the following sequence of writes… . . .