[Solved]1 Draw Synthesized Logic Resulting Following Vhdl Code Label Signals Diagram Precisely Ent Q37232051

problem 4 and 5

1. Draw the synthesized logic resulting from the following VHDL code. Label all the signals on your diagram precisely entity unknown is generic (k: natural: 3) port (x in std_logic_vector (2″k-1 downto 0); f: out std logic); end unknown; architecture struct of unknown is component and2 is port (a, b: in std_logic; c: out std_logic) end component component or2 is port (a, b: in std_logic; c: out std_logic) end component type matrix is array (k-1 downto 0, 2″k-1 downto 0) of std_logic; signal temp matrix; begin outer_loop: for j in k-1 downto 0 generate inner_loop: for i in 0 to 2j-1 generate and gen: ifj k-1 then generate and gate: and2 port map (X(2*i), X(2*i1), tempii)): end generate; or gen: if j <k-1 then generate or gate: or2 port map (tempj+1,2″i), temp+1,2i1), tempi)) end generate; end generate; end generate; ftemp(0,0): end struct; 2. What is the critical path delay for the circuit in problem 1 based on your diagram in a general case? State your answer in terms of variables used in the design assuming the delay of AND and OR gates are TAND and Tos respectively. 3. Consider the signal X having the waveform as follows. Draw the output waveform (Z) if X is applied at the input of a buffer element specified as: a) 2transport X after 15 ns b)2Xafter 15 ns c) 2-reject 7 ns inertial X after 25 ns Show transcribed image text 1. Draw the synthesized logic resulting from the following VHDL code. Label all the signals on your diagram precisely entity unknown is generic (k: natural: 3) port (x in std_logic_vector (2″k-1 downto 0); f: out std logic); end unknown; architecture struct of unknown is component and2 is port (a, b: in std_logic; c: out std_logic) end component component or2 is port (a, b: in std_logic; c: out std_logic) end component type matrix is array (k-1 downto 0, 2″k-1 downto 0) of std_logic; signal temp matrix; begin outer_loop: for j in k-1 downto 0 generate inner_loop: for i in 0 to 2j-1 generate and gen: ifj k-1 then generate and gate: and2 port map (X(2*i), X(2*i1), tempii)): end generate; or gen: if j

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Answer to 1. Draw the synthesized logic resulting from the following VHDL code. Label all the signals on your diagram precisely en… . . .