[Solved]3 4 Stage Pipeline Suffers Memory Access Resource Conflict Shown Instruction 2 Want Access Q37160368

3) The 4-Stage Pipeline below suffers from the memory accessresource conflict as shown below (instruction i and i+2 want toaccess memory at the same time and i+2 needs to be denied, so itwaits for the next cycle; in the next cycle it has a conflict withi+1 so it stalls for another cycle).

With one memory, a data and an instruction fetch cannot be initiated in the same clock FIDA FO EX i+1 iトッ stall stall FIDA FO EX The Pipeline is stalled for resource conflict HW PROBLEM 3: What is the speed up if we had the resource conflict mentioned above and the following pipeline stages: [1] FI: Fetch an instruction from memory (4 ns) 2] DA: Decode the instruction and calculate the effective address of the operand (2 ns) 3] FO: Fetch the operand (4 ns) [4] EX: Execute the operation (3 ns) Show transcribed image text With one memory, a data and an instruction fetch cannot be initiated in the same clock FIDA FO EX i+1 iトッ stall stall FIDA FO EX The Pipeline is stalled for resource conflict HW PROBLEM 3: What is the speed up if we had the resource conflict mentioned above and the following pipeline stages: [1] FI: Fetch an instruction from memory (4 ns) 2] DA: Decode the instruction and calculate the effective address of the operand (2 ns) 3] FO: Fetch the operand (4 ns) [4] EX: Execute the operation (3 ns)

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Answer to 3) The 4-Stage Pipeline below suffers from the memory access resource conflict as shown below (instruction i and i+2 wan… . . .