[Solved] ECE 410: Homework- Problem 1- 5

Problem 1
a) In Cadence, construct the schematic for a 6T SRAM cell with all transistors minimum sized.
b) Setup a stimulus file wherein bit is initialized to ground and bit_bar to VDD. Then switch bit to VDD and bit_bar to ground where they will remain. Connect the word line to a voltage source that switches from low to high after the final bit/bit_bar values are set. Measure the rise time of the internal node connected to bit through the access transistor. Record this value as the SRAM write delay.
c) Check the fall time of the other internal node (connect to bit_bar) when wordline is turned on and comment on any differences in this value and that from part (b). What circuit parameter could you change to make these values match?
d) Increase the size of both access transistors by a factor of two and repeat parts (b) and (c). Comment on the differences in the SRAM write delay for two different access transistor sizes.
Problem 2
The storage capacitor in a DRAM has a value of CS = 75fF. The circuitry restricts the capacitor voltage to a value of Vmax = 2.5 V. When the access transistor is off, the leakage current of the cell is estimated to be 5nA.
a) How many electrons can be stored on Cs?
b) How many fundamental charge units q leave the cell in 0.1 second due to leakage current?
c) Calculate the time needed to completely discharge the storage capacitor through leakage current.

Problem 3
Consider a DRAM cell that has a storage Cs=75fF, Vdd=3.0V, and Vth=0.65V. The leakage current from the storage capacitor is estimated to be 500pA. The capacitor has a voltage Vmax across it when the word line is brought low at time t=0.
a) Calculate the time it takes to discharge the capacitor to 1.0V.
b) Assuming the leakage current is constant for all values of storage capacitor voltage and that the minimum readable stored voltage is 1V, plot the DRAM hold time as a function of leakage current.
c) From your plot, estimate the maximum leakage allowed for a hold time of 1msec.
d) What is the required refresh rate for the conditions in part (c)?
e) Assuming that Vs = 2.5V, what is the maximum bit-line capacitance, C bit, that will provide a logic high output to be read with at least 0.25V on the bit line?

Problem 4
Draw the schematic for a circuit that will ensure an SRAM with two write ports is never written by both inputs at the same time. If both write line signals are active, your circuit should either disable both or allow only one to write (prioritized).

Problem 5
Sketch the transistor-level schematics for the following basic logic gates using domino logic (not static CMOS): INV, AND, OR, XOR.

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Answer to ECE 410: Homework- Problem 1- 4….