[Solved] 20 Points Following Architecture Multicycle Pipeline 32 Bit Five Stages Starting Instructi Q37239082

(20 Points): The following architecture is for a multicycle (pipeline) 32-bit. It has five stages starting from Instruction fetch to write back to the register- file. In Furthermore, the memory part cannot read and write at the same time. Redesign the register file part to be able to read/write and the same time to allow processor to be running in six stages instead of five using a description language as Verilog HDL. Furthermore, in term of performance, which is the best, to have five or six stages of pipeline depth? processor 5. processor, the register file cannot read and write and the same time. WB: Write back MEM: Me mory access EX: Execute / address calcula tio n ID Instructio n decodel register file read IF: In stru ctio n fetch Add Add Shilt regsbr 1 Read regisr2 Read data 1 Address PC Zero ALU ALU Regiaters Read data 2 Instruetion Address egser Data Insruction menary memony data Wite 12 Gign processor has 64 32-bit general purpose registers (GPR), represented as S0, $1, Note: $63, the content of $0 is always 0. Show transcribed image text (20 Points): The following architecture is for a multicycle (pipeline) 32-bit. It has five stages starting from Instruction fetch to write back to the register- file. In Furthermore, the memory part cannot read and write at the same time. Redesign the register file part to be able to read/write and the same time to allow processor to be running in six stages instead of five using a description language as Verilog HDL. Furthermore, in term of performance, which is the best, to have five or six stages of pipeline depth? processor 5. processor, the register file cannot read and write and the same time. WB: Write back MEM: Me mory access EX: Execute / address calcula tio n ID Instructio n decodel register file read IF: In stru ctio n fetch Add Add Shilt regsbr 1 Read regisr2 Read data 1 Address PC Zero ALU ALU Regiaters Read data 2 Instruetion Address egser Data Insruction menary memony data Wite 12 Gign processor has 64 32-bit general purpose registers (GPR), represented as S0, $1, Note: $63, the content of $0 is always 0.

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Answer to (20 Points): The following architecture is for a multicycle (pipeline) 32-bit. It has five stages starting from Instruct… . . .