[Solved]74181 Able Handle 4 Bit Addition Wanted Perform 16 Bit Addition Could Tie Cn 4 Ports Lower Q37184169
We were unable to transcribe this imageEach 74181 is able to handle 4-bit addition. If we wanted to perform a 16-bit addition, we could tie the Cn+4 ports of lower order 74181s to the cn ports of higher order 74181s, rippling the carries between each unit. While internally each unit does a carry-lookahead addition, carries are still rippled between units. We can do better by using the 74182, which takes the group generates and propagates, G and P, from the 74181s and produce the carries that are fed into the cns of the 74181s. Note that the 74181s Gs and Ps rely only on A3…Ao and B3.. .Bo: the 74182 produces carries using these Gs and Ps and the initial carry in. Here is an annotated example schematic of 16-bit addition made out of 74181s and a 4182, found in TI’s 74182 datasheet: า3181.ร 下 G7,A c4 G118 G3.0 $182 Leftmost 74181 is the lowest order, rightmost is the highest order (this was back in the day when MSB being the leftmost hadn’t been settled on yet) (TI made a typo: the 3rd on should not have a bar over it) Since we’re simplifying these parts for this problem, treat all the signals as active high The ports of interest on the 74182 are G, G, Рз Po. G, P, cn, Cn+x. Cn+y and cn+2. Inputs G3… Go and P3..Po are group generates and propagates from 74181s or other 74182s. Outputs G and P are the group generate and propagate that aggregate the input group generates G3… Go. group propagates Ps… Po, and the base carry in cn. G and P can be fed into more 74182s For example, if Gs were G15,12, G2 were G11,8. Gı were G7,4, and Go were G3,0, G would be G1s Input cn is the base carry in Outputs cn+x, Cn-ty, and on+z are the carries calculated by the 74182. For now you can think of them as Cn+4, Cn+8, and cn+12. (x, y, and z make more sense when we see the 64-bit adder). For example, if cn receives Co, ntx Corresponds to cs Cnty corresponds to cs, and Cntz corresponds to c12. Let’s analyze the 74182 logic: e. [5] In terms of G3… Go, Ps…Po, and n, derive SOP equations for G, P, Cntx, Cn-ty and ntz. f. [5] Calculate the delays for G, P, Cntx, Cnty and z relative to G3…Go, P.. Po, and cn’s arrival at t-0 g. [5] Rippling 74181s for a 16-bit adder, what is the delay for c16 relative to the arrivals of A15…Ao Bi5..Bo, and co at t-0? h. [5] Using 74181s in conjunction with a 74182 for a 16-bit adder, what is the delay for ci6 relative to the arrivals of A1s…Ao. B15…Bo, and co at t-0? By connecting 4 of these 16-bit adders to another 74182, we can create a 64-bit adder. Here is an annotated schematic of the 3-level 64-bit addition found in TI’s 74182 datasheet LS181, S181, “S281. “S381, or “$481 631,28 627.24 G15.12 G19.16 G7.4 611.8 G3.0 e36 24 C28 c12 20 c8 $182 S182 $182 G31.16 c16 c32 G15.0 $182 Pictured is only part of the full 64-bit setup: the schematic is more to show the 3-level structure. (The 16-bit adder figure was actually cropped from this one) i. [5] Rippling 74181s for a 64-bit adder, what is the delay for 4 relative to the arrivals of A63…A B63…Bo, and co at t-0? j. [5] Using a 3-level setup of 74181s and 74182s for a 64-bit adder, what is the delay for cs4 relative to the arrivals of A63…Ao, B63… Bo, and co at t- 0? Show transcribed image text
Each 74181 is able to handle 4-bit addition. If we wanted to perform a 16-bit addition, we could tie the Cn+4 ports of lower order 74181s to the cn ports of higher order 74181s, rippling the carries between each unit. While internally each unit does a carry-lookahead addition, carries are still rippled between units. We can do better by using the 74182, which takes the group generates and propagates, G and P, from the 74181s and produce the carries that are fed into the cns of the 74181s. Note that the 74181s Gs and Ps rely only on A3…Ao and B3.. .Bo: the 74182 produces carries using these Gs and Ps and the initial carry in. Here is an annotated example schematic of 16-bit addition made out of 74181s and a 4182, found in TI’s 74182 datasheet: า3181.ร 下 G7,A c4 G118 G3.0 $182 Leftmost 74181 is the lowest order, rightmost is the highest order (this was back in the day when MSB being the leftmost hadn’t been settled on yet) (TI made a typo: the 3rd on should not have a bar over it) Since we’re simplifying these parts for this problem, treat all the signals as active high The ports of interest on the 74182 are G, G, Рз Po. G, P, cn, Cn+x. Cn+y and cn+2. Inputs G3… Go and P3..Po are group generates and propagates from 74181s or other 74182s. Outputs G and P are the group generate and propagate that aggregate the input group generates G3… Go. group propagates Ps… Po, and the base carry in cn. G and P can be fed into more 74182s For example, if Gs were G15,12, G2 were G11,8. Gı were G7,4, and Go were G3,0, G would be G1s Input cn is the base carry in Outputs cn+x, Cn-ty, and on+z are the carries calculated by the 74182. For now you can think of them as Cn+4, Cn+8, and cn+12. (x, y, and z make more sense when we see the 64-bit adder). For example, if cn receives Co, ntx Corresponds to cs Cnty corresponds to cs, and Cntz corresponds to c12. Let’s analyze the 74182 logic: e. [5] In terms of G3… Go, Ps…Po, and n, derive SOP equations for G, P, Cntx, Cn-ty and ntz. f. [5] Calculate the delays for G, P, Cntx, Cnty and z relative to G3…Go, P.. Po, and cn’s arrival at t-0 g. [5] Rippling 74181s for a 16-bit adder, what is the delay for c16 relative to the arrivals of A15…Ao Bi5..Bo, and co at t-0? h. [5] Using 74181s in conjunction with a 74182 for a 16-bit adder, what is the delay for ci6 relative to the arrivals of A1s…Ao. B15…Bo, and co at t-0?
By connecting 4 of these 16-bit adders to another 74182, we can create a 64-bit adder. Here is an annotated schematic of the 3-level 64-bit addition found in TI’s 74182 datasheet LS181, S181, “S281. “S381, or “$481 631,28 627.24 G15.12 G19.16 G7.4 611.8 G3.0 e36 24 C28 c12 20 c8 $182 S182 $182 G31.16 c16 c32 G15.0 $182 Pictured is only part of the full 64-bit setup: the schematic is more to show the 3-level structure. (The 16-bit adder figure was actually cropped from this one) i. [5] Rippling 74181s for a 64-bit adder, what is the delay for 4 relative to the arrivals of A63…A B63…Bo, and co at t-0? j. [5] Using a 3-level setup of 74181s and 74182s for a 64-bit adder, what is the delay for cs4 relative to the arrivals of A63…Ao, B63… Bo, and co at t- 0?
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Answer to Each 74181 is able to handle 4-bit addition. If we wanted to perform a 16-bit addition, we could tie the Cn+4 ports of l… . . .
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